The present invention involves digital data bus systems.
Systems such as consumer electronics systems typically include various devices, such as integrated circuits, that are coupled together using a data bus for communicating information between the devices. An example of this type of system is a television receiver which includes an I2C serial data bus for communicating tuning data from a control microprocessor to a tuner causing the tuner to tune a particular channel. An I2C data bus is a well known serial data bus comprising two bus lines, a clock line designated SCL and a serial data line designated SDA, that carry information between devices connected to the bus. Each device is assigned a unique address permitting communications on the bus to be directed to a particular device. Each device can transmit data, receive data, or both as required by the function of the device. In addition to transmitting and receiving data, each device can also function as a master or slave when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.
The I2C bus is a multi-master bus, meaning that more than one device is capable of controlling the bus. Masters are usually control devices such as microprocessors, microcomputers, or microcontrollers (also referred to herein as xe2x80x9ccontrollersxe2x80x9d). The possibility of connecting more than one microcontroller to the bus means that more than one master can try to initiate a data transfer at the same time on the bus. A procedure known as arbitration favorably resolves such an event. Arbitration relies on the wired-AND connection of all I2C interfaces to the bus. Should two or more masters try to place information on the bus, the first one to produce a logic one when the other produces a logic zero will lose the arbitration. The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired-AND connection to the SCL line. The specification for the I2C bus protocol specifies that the output stages of devices connected to the bus are to have an open-drain or open-collector in order to perform the wired-AND function. Consequently, pull-up of the bus lines is usually accomplished through pull-up resistors connected between the bus lines and a source of supply voltage.
Generation of clock signals on the I2C bus is always the responsibility of the master devices. Each master generates its own clock signal when transferring data on the bus. Data is only valid during the logic high period of the clock. Bus clock signals from a master can only be altered by another master when arbitration occurs or when the clock signals are stretched by a slow-slave device holding down the clock line. For example every byte of information put on the SDA line (i.e., 8 bits of information) must be followed by an acknowledge bit. An acknowledge-related clock pulse is generated by the master. During the acknowledge clock pulse, the transmitter releases the SDA line and the receiver must pull down the SDA line. A receiving device can delay receipt of another byte of data, e.g., until it has performed some other function such as servicing an interrupt, by holding the SCL clock line low which will force the transmitting device into a wait state. U.S. Pat. No. 4,689,740 issued to Adrianus P. M. M. Moelands and Herman Schutte details the operation of the I2C bus and protocol.
The invention resides, in part, in recognizing that while the relative simplicity and availability of numerous compatible devices make a bus protocol such as I2C desirable, the form of bus driver associated with the bus protocol may not be adequate for certain applications. For example, bus drivers used with an I2C bus system typically use an open collector (or drain) device with a pull-up resistor coupled between the bus line and a source of reference voltage. Capacitive loading of a bus line combined with the resistance of a pull-up resistor may significantly degrade the speed at which a bus line can be pulled up. Further, capacitive loading increases with the number of devices coupled to the bus. This can pose a problem for applications that require high speed and involve high capacitive loads such as during production testing of a device incorporating bus driver capability (note that the term xe2x80x9cdevicexe2x80x9d as used herein includes integrated circuits and apparatus such as television receivers). Furthermore, the master has numerous other tasks to perform besides communicating with the slave devices. Therefore, a need exists for a bus driver suitable for driving buses such as an I2C bus with large loads at high speed to perform the communication between master and slave devices as fast as possible.
In addition, the inventor has recognized that utilizing a modified form of bus driver that can drive large loads at high speeds may be incompatible with existing bus compatible devices. In particular, existing I2C compatible devices are designed with current sinking capability sufficient only to pull down a bus line held high by a pull-up resistor (e.g., during an acknowledge interval or to cause a wait state). Such current sinking capability may be inadequate to pull down a bus line driven by a high speed driver circuit.
Also, the inventor has recognized that while it may be desirable to communicate data at high data rates across a heavily loaded bus, doing so may produce undesirable noise effects. Driving data across a data bus at high data rates involves using fast signal edges that have high frequency harmonic components. For example, in a television system, these high frequency harmonics can introduce noise into the video signal processing channel and may cause undesirable noise effects in a displayed video image.
The invention also resides, in part, in providing an apparatus for coupling data to a data bus that solves the described problems. More specifically, apparatus constructed in accordance with one aspect of the invention comprises a data bus, a passive device for changing a signal on the data bus between first and second states at a first rate during a first mode of operation, and an active device enabled during a second mode of operation for changing the signal between the first and second states at a second rate different than the first rate. The second mode of operation may correspond to a particular condition of the bus such as an acknowledge condition or a data read condition.
In accordance with another aspect of the invention, information generated by a device is coupled to an I2C data bus via a push-pull device. Another aspect of the invention involves the push-pull device having first and second modes of operation. During the first mode of operation, the push-pull device couples information to the I2C data bus at a first rate. During the second mode of operation, the push-pull device couples information to the I2C data bus at a second rate.
In accordance with another aspect of the invention, the apparatus comprises a coupling device for coupling data to a data bus and a timing signal generator for generating a timing signal indicating first and second portions of a television signal. The coupling device is controlled by a control device in response to the timing signal such that the coupling device couples data to the data bus at a first rate during the first portion of the television signal and couples data to the data bus at a second rate during the second portion of the television signal. The first portion of the television signal may comprise an active video interval while the second portion of the television signal may comprise a blanking interval. The first rate at which data is coupled to the data bus may be less than the second rate at which data is coupled to the data bus. A push-pull device included in the coupling device can be disabled during the first portion of the television signal and enabled for driving data onto the data bus at the second rate during the second portion of the television signal.